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Fri 22 Jan 2016 10:30 - 10:55 at Grand Bay South - Track 2: Semantics and memory models Chair(s): Alexey Gotsman

In this paper we develop semantics for key aspects of the ARMv8 multiprocessor architecture: the concurrency model and much of the 64-bit application-level instruction set (ISA). Our goal is to clarify what the range of architecturally allowable behaviour is, and thereby to support future work on formal verification, analysis, and testing of concurrent ARM software and hardware.

Establishing such models with high confidence is intrinsically difficult: it involves capturing the vendor’s architectural intent, aspects of which (especially for concurrency) have not previously been precisely defined. We therefore first develop a concurrency model with a microarchitectural flavour, abstracting from many hardware implementation concerns but still close to hardware-designer intuition. This means it can be discussed in detail with ARM architects. We then develop a more abstract model, better suited for use as an architectural specification, which we prove sound w.r.t.~the first.

The instruction semantics involves further difficulties, handling the mass of detail and the subtle intensional information required to interface to the concurrency model. We have a novel ISA description language, with a lightweight dependent type system, letting us do both with a rather direct represention of the ARM reference manual instruction descriptions.

We build a tool from the combined semantics that lets one explore, either interactively or exhaustively, the full range of architecturally allowed behaviour, for litmus tests and (small) ELF executables. We prove correctness of some optimisations needed for tool performance.

We validate the models by discussion with ARM staff, and by comparison against ARM hardware behaviour, for ISA single- instruction tests and concurrent litmus tests.

poster (poster.pdf)411KiB

Fri 22 Jan

Displayed time zone: Guadalajara, Mexico City, Monterrey change

10:30 - 12:10
Track 2: Semantics and memory modelsResearch Papers at Grand Bay South
Chair(s): Alexey Gotsman IMDEA
Modelling the ARMv8 Architecture, Operationally: Concurrency and ISA
Research Papers
Shaked Flur University of Cambridge, Kathryn E. Gray University of Cambridge, Christopher Pulte University of Cambridge, Susmit Sarkar University of St Andrews, Luc Maranget INRIA Rocquencourt, Ali Sezgin University of Cambridge, Will Deacon ARM Ltd., Peter Sewell University of Cambridge
Media Attached File Attached
A concurrency semantics for relaxed atomics that permits optimisation and avoids thin-air executions
Research Papers
Jean Pichon-Pharabod University of Cambridge, Peter Sewell University of Cambridge
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Overhauling SC atomics in C11 and OpenCL
Research Papers
John Wickerson Imperial College London, Mark Batty University of Cambridge, Alastair F. Donaldson Imperial College London
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Taming Release-Acquire Consistency
Research Papers
Ori Lahav MPI-SWS, Nick Giannarakis MPI-SWS, Viktor Vafeiadis MPI-SWS, Germany
Pre-print Media Attached File Attached